1. Field of the Invention
The present invention relates to a method of manufacturing a flash memory device, and more particularly to a method of manufacturing a flash memory device capable of reducing a difference in effective field oxide heights (“EFH”) between a high voltage transistor area, and a low voltage transistor/cell area, which is caused by respective protruding portions of element isolation films thereon in a flash memory device manufactured by applying a self-align shallow trench isolation (“SA-STI”) scheme.
2. Discussion of Related Art
Basically, a flash memory device has low voltage transistors and high voltage transistors in order to drive cells according to necessary properties. Usually, a gate oxide film for the high voltage transistor is made to be thick, on the other hand, in case of the low voltage transistor, it is made to be thin. The thickness of a gate oxide film for a cell is equal or similar to that for a low voltage transistor. The steps caused by a difference in thickness of the gate oxide films between the high voltage transistor area and the low voltage transistor/cell area result in different thickness of the nitride films which remain after the subsequent chemical mechanical polishing for forming the element isolation films in each of areas. Also, this generates a difference in EFH's between the high voltage transistor area and the low voltage transistor/cell area. Herein, the EFH means a difference in heights of the element isolation films based on the contact surface of a first poly-silicon layer for a floating gate and a second poly-silicon layer for a floating gate.
Shown in FIG. 1 is a cross-sectional view illustrating a conventional method of manufacturing a flash memory device formed by applying a self-align shallow trench isolation scheme. Although a flash memory device includes a cell area, a low voltage transistor area, and a high voltage transistor area, the cell area and the low voltage transistor area will be considered as one area—the low voltage transistor/cell area—in the following descriptions for easier understanding because the thickness of their gate oxides is similar to each other.
Referring to FIG. 1, a gate oxide film 12A for a high voltage is formed on a semiconductor substrate 11 in a high voltage transistor area HV, and another gate oxide film 12B for a low voltage/cell is formed on a semiconductor substrate 11 in a low voltage transistor/cell area LV/CELL. The gate oxide film 12A in a high voltage transistor area HV is thicker than the gate oxide film 12B in a low voltage transistor/cell area LV/CELL. A first poly-silicon layer 13 for a floating gate is formed on the gate oxide films 12A and 12B. A plurality of isolation trenches are formed on the semiconductor substrate 11 by performing an SA-STI process. Thereafter, element isolation films 160 are formed by filling isolation oxide materials into the trenches 15. A second poly-silicon layer 19 for a floating gate is formed on the whole surface of the structure, including the element isolation films 160. Although it is not shown in the drawing, gates are formed on respective areas by performing an etching process using a mask for a floating gate, a process of forming a dielectric film, a process of forming a conductive layer for a control gate, and an etching process using a mask for a control gate.
According to the conventional method of manufacturing a flash memory device described above, each of protruding portions of element isolation films 160 in the high voltage transistor area HV and the low voltage/cell area LV/CELL causes a difference in EFH's between these areas. Generally, the effective field oxide height EFH1 based on the first poly-silicon layer 13 in the high voltage transistor area HV becomes (−) 50 to 100 Π, whereas the effective field oxide height EFH2 based on the first poly-silicon layer 13 in the low voltage transistor/cell area LV/CELL becomes in the range of 300 Π to 800 Π. The effective field oxide height EFH2 in the low voltage transistor/cell area LV/CELL has a higher and wider range of values. Furthermore, the values become different depending on the processing conditions of a chemical mechanical polishing. Such a difference in EFH's between the high voltage transistor area HV and the low voltage transistor/cell area LV/CELL and the high value of EFH's in the low voltage transistor/cell area LV/CELL, causes some problems such as difficulties in establishing a gate etching target for each area, bad pattern profiles of the gate, and reasons of failures caused by the poly-silicon remnants. Since these problems become important as devices are highly integrated, continuous efforts have been made to solve them.